The present invention relates to a semiconductor device and a manufacturing technology thereof, in particular, to an element isolation structure for electrically isolating high breakdown voltage semiconductor elements formed on the main surface of an SOI (silicon on isolation) substrate and a technology effective when applied to the manufacture of the structure.
In recent years, trench isolation has been employed in order to electrically isolate two adjacent semiconductor elements provided on the main surface of a semiconductor substrate, because it can provide a surface of almost the same level as that of the main surface of the semiconductor substrate and at the same time, it enables more minute processing than LOCOS (local oxidation of silicon) isolation. Trench isolation is formed by forming a trench in the main surface of a semiconductor substrate and then burying an insulating film in the trench.
For example, Japanese Patent Laid-Open No. 2002-43413 (Patent Document 1) discloses a forward tapered trench formed using anisotropic etching at a position near the surface of a semiconductor substrate and another trench, which lies therebelow and is coupled thereto, formed by isotropic etching so that the width of its bottom portion is equal to or greater than the width of the bottom of the forward tapered trench.
Japanese Patent Laid-Open No. 2008-60383 (Patent Document 2) discloses a technology of, after formation of a trench in the surface of a silicon substrate, isotropically etching the inner surface of the trench with radicals in order to clean the inner surface of the trench to remove contaminants therefrom and remove a defect layer on the inner surface of the trench.
Japanese Patent Laid-Open No. 2009-99815 (Patent Document 3) discloses semiconductor device capable of providing a common potential between wells by forming a trench between wells of the same kind, forming a silicide layer at least on the bottom of the trench, and coupling these wells of the same kind at low resistance. The trench is formed by patterning a semiconductor substrate by using anisotropic etching and then widening the opening width by using isotropic etching.
Japanese Patent Laid-Open No. 2008-306003 (Patent Document 4) discloses a technology of forming on a semiconductor substrate a trench having an aspect ratio of 10 or greater by using anisotropic dry etching and then removing a damage layer by isotropic dry etching from the whole wall surface of the trench.
Japanese Patent Laid-Open No. 40666/1999 (Patent Document 5) discloses a technology of forming, between two wirings adjacent to each other, an interlayer insulating film comprised of a silicon oxide film having a pore and a low dielectric constant insulating film formed thereon in order to reduce a capacitance between wirings of the same layer or different layers.
Japanese Patent Laid-Open No. 2007-110119 (Patent Document 6) discloses a technology of forming a first layer of a first insulating substance by using plasma chemical vapor deposition so as to provide a space between two adjacent wirings and after causing the first layer to retreat, depositing a second layer of a second insulating substance on the resulting first layer.
Japanese Patent Laid-Open No. 2000-150807 (Patent Document 7) discloses a technology of suppressing a dishing phenomenon by rounding or tapering the corner of a trench having a substantially polygonal shape to surround therewith an element region.
International Patent Publication No. 2009-518838 (Patent Document 8) discloses the structure of insulating trenches having a uniform insulating trench width obtained by chamfering or rounding the trenches at a cross region or confluent region thereof and placing a center island in the cross region or confluent region to make the width of the insulating trenches in the cross region or confluent region equal to that of the insulating trenches in a region other than the cross region or confluent region.    [Patent Document 1] Japanese Patent Laid-Open No. 2002-43413    [Patent Document 2] Japanese Patent Laid-Open No. 2008-60383    [Patent Document 3] Japanese Patent Laid-Open No. 2009-99815    [Patent Document 4] Japanese Patent Laid-Open No. 2008-306003    [Patent Document 5] Japanese Patent Laid-Open No. 40666/1999    [Patent Document 6] Japanese Patent Laid-Open No. 2007-110119    [Patent Document 7] Japanese Patent Laid-Open No. 2000-150807    [Patent Document 8] International Patent Publication No. 2009-518838